How store-to-load forwarding selects older buffered bytes

A load can need the value of an earlier store even though that store has not updated the cache yet. Reading the old cache contents would miss the pending value, so a processor can supply the load directly from an older buffered store.

store-to-load forwarding is that local handoff under a specified implementation model. Correctness depends on the newest preceding supplier for each requested byte, while the supported forwarding shapes determine whether the load can proceed immediately or must wait.

The examples use symbolic byte addresses, explicit operation ages and hypothetical forwarding paths. They make no claim about a listed processor's particular penalties or undocumented forwarding rules.

Place older values in the store buffer

Let cache bytes at addresses 100 through 103 initially contain [0,1,2,3]. A store S1 precedes load L in the program's applicable order. S1 writes four bytes [10,11,12,13] to those same addresses.

Stipulate that S1's address, width and data are known, but its update has not yet reached the cache. Its pending entry identifies start address 100, width four, data [10,11,12,13] and age one.

Load L has age two and requests four bytes starting at 100. Under the model's local ordering requirement, it needs S1's values for those bytes. The old cache data remains [0,1,2,3] until the pending store propagates.

A forwarding path that accepts this same-address, same-width match can return [10,11,12,13] from S1's entry. That satisfies this local load without waiting for the cache update.

The DMA guide provides a consuming-view comparison for a store buffer. Its noncoherent device can read backing zero while the CPU sees current cached one. That device path differs from this buffered local store, but the example reinforces why a successful read at one boundary cannot certify propagation at another. Here L can receive the required bytes directly while S1's cache update remains pending. The DMA guide supplies no store-forwarding implementation or universal timing rule.

Operation age identifies which stores precede L under the contract. A newer store that comes after L cannot supply its value merely because an implementation happens to have data for that store available.

Separate the forwarded result from a cache update

After the handoff, L has the required four-byte result, but the cache can still contain the old bytes in the stipulated timeline. The forwarding result is not a receipt that S1 has propagated into every other storage boundary.

The pending store must later follow the implementation's update and ordering rules. L's successful local result does not remove that obligation. Likewise, another core's observation cannot be inferred from L's result. The example concerns one local older-store-to-younger-load relationship; cross-core visibility and publication need a separate memory contract.

A trace should therefore keep the store-buffer entry, load result and cache-update event distinct. Calling all three memory updated would erase the mechanism that let L proceed early.

Determine suppliers for overlapping memory accesses

Now give S1 age one and the same four-byte write at addresses 100 through 103. Add store S2 at age two, writing [20,21] only at addresses 102 and 103. Load L has age three and requests all four bytes.

For address 100, the newest preceding matching store is S1, supplying 10. For 101, S1 supplies 11. For 102 and 103, S2 is newer than S1 but still older than L, so S2 supplies 20 and 21. The required result is therefore [10,11,20,21]. Returning S1's whole four-byte data would be wrong for the two bytes superseded by S2. Returning S2 alone would be incomplete because it covers only half of L's range.

Apply the rule to each byte: choose the newest applicable preceding store covering each requested byte, under the known addresses, widths and ordering assumptions. A matching start address alone does not establish complete coverage.

The linearizability guide gives an order-and-result comparison for overlapping memory accesses. Its queue outcomes are judged against explicit operation histories and a supplied sequential contract; a conveniently available result is insufficient when it contradicts those constraints. Our byte suppliers likewise depend on L's position and the stipulated ordering rule. The queue proof neither defines store-buffer hardware nor makes speculative memory operations into completed public queue calls.

If an applicable store's data is not ready, knowing its range does not provide its byte value. The implementation must obey the local result contract rather than use an older superseded value just because that older value is available.

Compare a full forwarding path with a restricted one

Stipulate a full forwarding path that can select and combine bytes from several older entries. It can construct [10,11,20,21] for the two-store example when both entries' required information is ready.

Now stipulate a restricted path that forwards only from one older store when that entry covers the entire load in the supported shape. The first same-address four-byte example qualifies, while the two-entry merged result does not.

The restricted path still owes L the same correct answer, even though it cannot obtain it through that immediate merge. Under this model, the unsupported merged load must wait until the required values become available through another permitted path. For example, let S1 and then S2 update the cache according to their applicable order. The cache first receives [10,11,12,13], then its final two bytes become [20,21]. L can subsequently read [10,11,20,21] through the stipulated cache path.

A restricted forwarder cannot return [10,11,12,13] as a successful shortcut while S2 remains the required newer supplier. Its shape limitation does not relax the program-visible byte relationship.

Actual implementations can support other combinations and have additional readiness conditions. The example's full and restricted paths are explicit models, not descriptions of every processor.

Untouched bytes can come from another permitted source

Use another range example: S1 writes two bytes [10,11] at 100 and 101, while L requests four bytes at 100 through 103. No other preceding buffered store covers 102 or 103 in this model.

For the first two bytes, S1 is the required supplier. The remaining two bytes still need their applicable memory source. If the current permitted cache contents there are 2 and 3, the required full result is [10,11,2,3]. A path supporting a buffer-and-cache merge can obtain that result under its readiness rules. A path without that merge can wait for S1's cache update and then use the resulting cache data.

The selected sources need to account for the same load range and ordering conditions. Combining any ready bytes without that relationship would not establish correctness.

This trace also avoids confusing a load's width with one store's width. The requested bytes define what must be supplied; several sources may be needed even when one entry's start address matches.

Widths, ranges, and ages are separate inputs

A later entry illustrates the age filter. Suppose S3 has age four and writes [30,31,32,33] across [100,104), while L still has age three. S3 may have available data under a hypothetical execution path, but it is not an applicable preceding supplier for L. Choosing the newest physically present entry without checking L's ordering position would incorrectly return S3's values. The required L result remains [10,11,20,21] from S1 and S2 under this contract.

A useful entry description includes the operation's start address, byte width, data readiness and relative age. Omitting width can conceal partial coverage; omitting age can choose an inapplicable or superseded supplier.

Two entries can overlap without sharing a start address. S1's four-byte range [100,104) and S2's two-byte range [102,104) overlap in their final two byte positions. The half-open notation makes the covered addresses explicit.

Conversely, an entry with the same start address but a narrower width does not cover every byte of the four-byte load. The comparison needs the complete range rather than an address equality label.

Readiness affects progress after those suppliers are identified. An address-known entry with missing data and an address-unknown entry pose different missing prerequisites. Neither is justified as an immediate successful result by a merely present buffer slot.

Predictor mechanisms and recovery algorithms need another specification. This model identifies the source relationship required for a permitted load result.

Keep performance claims tied to a stated path

Waiting for an unsupported shape can delay this particular load under the restricted model. No numerical penalty follows from that statement without timing assumptions or a verified implementation measurement.

The same source-level access pattern can encounter different supported paths on different implementations. A four-byte match, multi-entry overlap or partial merge cannot be assigned a universal latency from its name.

A successful forwarded load also does not establish that the store completed every visibility obligation. Local data dependence and propagation remain distinct evidence even when the result arrives quickly.

The examples supply byte results and transition conditions; processor rankings or synchronization advice would require other evidence.

Verify every byte against its newest preceding supplier

Preserve the cache's initial bytes, older buffer entries and L's requested range. For each byte, list the newest applicable older store or the other permitted source when no entry covers it.

The two-entry example must return [10,11,20,21]. A proposed implementation path that returns the superseded 12 and 13 would fail that byte check even if it reports a forwarding hit.

For the restricted model, verify waiting rather than an incorrect shortcut and inspect the result once the required cache state is available. Keep that result separate from any claim about another core's view.

Inspect the source map with addresses 100 through 103 in separate columns using the Lenovo IdeaPad touchscreen laptop. The listing specifies a 15.6-inch FHD screen. Its native description identifies 16GB DDR4 alongside an i5-1334U processor and a 512GB PCIe SSD. Save S1 and S2 with their ages and widths, then mark S1 as supplier for 100 and 101 and S2 for 102 and 103. That table supports the declared byte trace; it does not measure the machine's forwarding path.

Keep the restricted path's wait beside its eventual cache result on the ASUS Vivobook 14 FHD laptop. The catalogue lists 16GB DDR4 memory and a Core 5 120U processor. Record the cache first becoming [10,11,12,13] and then [10,11,20,21] after the second store. A local forwarding result and those later cache updates remain separate evidence. No numerical delay follows from the product description.