How cache coherence locates current data and write permission

Several caches can hold one memory line while main memory is not always the location of its latest value. A core that modifies a line can become the owner of current data, and later reads must follow the protocol that identifies that owner.

cache coherence coordinates those permissions and copies. A cross-address publication rule must additionally specify when observing a flag establishes visibility of its associated data.

The examples define a simplified three-state protocol. They are not a description of a particular processor's undocumented implementation or a language-level synchronization recipe.

Define cache ownership through stable states

Use states Invalid, Shared and Modified for each cache's copy of one line. Invalid means the copy cannot supply a permitted read. Shared permits reading and, under this model, its contents match main memory.

Modified grants the current cache exclusive permission to change the line. Other caches have no valid copy under this stable-state contract. Main memory can remain older than the Modified contents.

A store to a Shared copy first needs the protocol's exclusive-write transition. The core cannot simply modify its local copy while another core continues using an earlier valid Shared value. The model coordinates the required invalidations and establishes ownership before admitting that store. The exact messages and bookkeeping are stipulated rather than attributed to a real chip.

These stable states describe allowed settled relationships. A full implementation would also need to define its in-progress transitions and races. Drawing a Modified label does not establish that all required ownership conditions have been completed.

Trace shared reads followed by a write request

Let main memory hold value zero for line L. Cores C0 and C1 each read it into their caches. Both copies are Shared, both contain zero, and main memory also contains zero.

C0 now wants to store one. It requests exclusive permission under the model. C1's Shared copy must become Invalid before the required ownership transition is complete.

Once the transition establishes C0 as the exclusive permitted writer, C0 stores one and holds L in Modified state. C1 cannot continue reading its old zero from the now-invalid local copy.

Main memory can still contain zero at this point. The protocol's current data is in C0. That relationship is consistent because a later requester must obtain the value through the coherence mechanism rather than treating old memory as authoritative.

The store's correct local completion therefore does not require an immediate update to main memory under this model. It does require the exclusive-permission and invalidation conditions that keep other valid copies from contradicting the current one.

Locate dirty cache lines when another core reads

C1 next requests a read of L. Its old copy is Invalid, so it cannot satisfy the request from that stale data. The model identifies C0 as holding the current Modified copy.

C0 supplies value one through the stipulated coherence transition. For this simplified protocol, the transition also writes one to main memory and leaves both caches in Shared state with value one. The resulting copies agree with main memory. Other protocol models could retain a different ownership state, but they would need their own definitions. This trace uses the stated three-state rules consistently.

The DMA guide supplies a consumer-path comparison for dirty cache lines. Its noncoherent device can read backing zero while the CPU retains dirty one; a declared coherent device path instead obtains current data through its specified relationship. Our CPU protocol explicitly makes C1's later read use that coherent relationship. The guide also separates visibility, command ordering and completed work, so a current cache value alone cannot certify a device handoff.

Dirty identifies a valid cache copy that differs from the backing copy under the write-back contract. The dirty owner can be the correct source of the current value.

A direct read of old backing bytes outside the stipulated coherence path would not establish a coherent CPU read result. The observation interface is part of the model, just as the permissions are.

Invalidation and writeback perform different operations

C1's invalidation during C0's ownership request removed C1's permission to use its earlier copy. It did not write C0's new value to main memory. C0 had not yet performed the new store when that invalidation occurred.

Writeback instead propagates current modified data to the backing location under the model's rule. The dirty copy contains information that must not be lost while it is the sole current source.

Consider C0 later relinquishing a Modified line. The transition must preserve its current contents in the required destination before that exclusive copy ceases to be authoritative. Simply changing its state to Invalid without preserving the value would violate the model.

An invalidation of a clean stale copy and preservation of a dirty current copy therefore have different obligations. Counting both as a cache message would conceal what each must accomplish.

A stable-state table makes an invalid combination visible. Initially C0 Shared0, C1 Shared0 and memory0 is permitted. After C0's store, C0 Modified1, C1 Invalid and memory0 is permitted. C0 Modified1 with C1 still Shared0 would violate the model because the old copy retained valid read permission. The invalid cache may physically retain old bits, but those bits cannot satisfy a permitted read while its state is Invalid.

The protocol evidence should identify permission changes and data transfers separately. Seeing a cache become Invalid does not supply a writeback receipt, and seeing memory updated does not alone establish that every other valid writer was excluded.

Follow the line's permitted readers and writer

For the initial state, C0 and C1 are readers of the same clean zero. During the store transition, C0 obtains exclusive writer permission and C1 loses its valid read copy. After the store, C0 holds current one and memory can be old zero. During the later read transition, the model transfers current data and returns the two caches to clean shared copies.

This trace identifies who may supply each read at each settled stage. The ownership state and applicable coherence action identify which present copy supplies the current value.

The history also needs the line identity. Copies for another address do not settle L's ownership. The numerical values alone cannot tell which copies belong to the same coherence unit.

Two addresses expose the publication-order boundary

Now use separate lines D for payload data and F for a ready flag. A producer's program requests setting D to 42 and then setting F to one. A consumer's program reads F and, if it observes one, reads D.

Per-line coherence alone does not specify the ordering relationship connecting those program requests and observations. It can supply a coherent order for D and another coherent order for F without supplying the intended publication path between them.

For an abstract candidate history, D's order places the consumer's read of old zero before the producer's D update becomes visible in that line's order. F's order places the producer's one before the consumer's flag read.

Each line's values can obey its own coherent order, yet the consumer sees F as one and D as zero. Whether an actual program may admit that candidate depends on the additional architectural and language ordering contract; it cannot be decided from the three coherence states alone.

The linearizability guide provides a specification-boundary comparison for cache ownership. It tests a complete public history against the sequential rules and mandatory real-time edges, rather than accepting isolated atomic instructions as sufficient evidence. Here the complete two-line publication history likewise needs its additional ordering contract. A valid owner for each separate line does not supply that contract. The queue guide proves neither hardware coherence nor a language memory model.

Record the two candidate orders explicitly: for D, consumer read returning 0 precedes producer write of 42; for F, producer write of 1 precedes consumer read returning 1. Those two orders each preserve the current value within their own line. If an added global contract also requires the producer's D write before its F write and the consumer's F read before its D read, all four edges form a cycle. That stronger contract rejects this candidate. The simplified coherence states alone do not include those cross-line edges.

The example does not permit an old read after the applicable D update in D's own coherent order. It identifies the missing constraint linking the two different line orders and program-level events.

Keep the protocol and wider memory contract explicit

The simplified ownership trace answers where L's current data lives and which copies may be used. It does not prove that every pair of addresses is observed in one global source-program order. Likewise, a publication relationship needs its own conditions for the payload and flag. The coherence model cannot fill them by treating the flag's latest value as an authorization to assume every other line changed first.

A full system can provide both coherence and specified ordering mechanisms. The review must identify the separate guarantees and their observation boundaries.

This article does not diagnose false-sharing layouts or prescribe synchronization syntax. The scope is the current-data and permission mechanism plus the boundary where its per-line argument stops.

Verify ownership transitions with current-value checks

Record main memory, each valid cache copy and the permission state for the same line. For C0's store, verify that C1's old copy becomes unusable before the model admits the exclusive write.

For C1's later read, verify the returned value one and the actual source relationship. An old-memory zero would fail the stated coherence trace even if C1's cache previously held that value.

Check invalidation and current-data preservation as separate effects. For the two-line case, preserve each line's order and the extra publication assumptions instead of treating one state label as proof of both.

Prepare the settled-state table using the Lenovo IdeaPad touch laptop, listed with a 15.6-inch FHD touchscreen. Its catalogue specifications include a 512GB PCIe SSD, 16GB DDR4 memory and an i5-1334U processor. Record C0's permission and value separately from C1's and main memory's. The row Modified1, Invalid, memory0 is valid here; Modified1 beside Shared0 is not. The hardware listing does not identify a real processor's exact protocol.

For reviewing the two-line candidate, the ASUS Vivobook 14 FHD laptop has a catalogue-listed Core 5 120U processor and 16GB DDR4 memory. Use its development workspace to keep D's read-before-write edge beside F's write-before-read edge. Add only the cross-line edges promised by the chosen system contract. Those explicit edges determine whether the combined history is admitted; a product specification cannot establish them.