How cache bank conflicts serialize resident accesses

Data being present in a cache does not establish that every ready access can be served at once. The requested service can concentrate on a bank or exceed its available ports even when none of the accesses misses.

cache bank conflicts concern that service boundary. A cache's resident capacity and its concurrent access capacity answer different questions, so zero misses need not imply one-round completion of a batch.

The examples define symbolic service addresses, bank mappings and round limits. They do not reveal a real processor's address hashing or measure a particular laptop's access latency.

Separate cache access ports from sets and residency

A set identifies the stipulated group of places in which a line can be resident under a cache's lookup rules. This model assumes every requested data unit is already resident and no request causes an eviction or fill.

A bank is a service partition holding the data under the selected mapping. A port supplies a stated capacity for requests serviced through that partition during one round. Use four banks named B0 through B3. Initially give each bank one read-service port, able to complete one model access per round. Different banks can serve their allowed requests in the same round.

Each access in the example uses one bank and one port for one round. All requests are ready at the start, and no extra issue or result-delivery limit constrains the batch. Those assumptions make the arithmetic explicit.

There is no request merging in this teaching model. A real implementation's wider accesses or merged service would need different rules. Resident-unit identities and service addresses are not asserted to be a real chip's cache-line layout.

The pipeline backpressure guide supplies a resource-accounting comparison for cache access ports. Its queue limit covers only queued work, while running tasks and retained outputs occupy other resources. Our resident-data account also covers one boundary; each requested service still needs its assigned bank's port. The pipeline guide does not define a cache scheduler. Both examples require the particular resource and its occupancy to be named before a total can support the intended bound.

Map every access to its service bank

Let a be a symbolic integer service address, and stipulate bank(a) equal to a modulo four. This is the example's complete mapping rule, not a claim about undocumented hardware bits.

For access pattern P, use addresses 0, 4, 8 and 12. Each has remainder zero, so all four requests need B0. B1, B2 and B3 receive no request from this batch.

For access pattern Q, use addresses 0, 1, 2 and 3. The requests map to B0, B1, B2 and B3 respectively. Each bank receives one request.

The initial resident data includes every unit requested by either pattern. Both batches contain four ready requests, and both have zero misses. Their bank demand differs despite those matched conditions.

A trace should preserve that mapping and the requested units. A miss counter or total request count cannot reconstruct which service bank each request needed.

Calculate rounds with one port per bank

Pattern P requires four services from B0, which has one port. The batch therefore needs four rounds under the stipulated capacity. One request can finish in each round while the other banks remain unused for this batch. Pattern Q can finish in one round because each of the four banks serves its one request concurrently. The model supplied no shared limit preventing those four independent bank services.

This difference is not a trip to lower memory or a replacement-policy consequence. The data is resident in both histories. The requested service distribution creates the serialization.

For these ready, single-round accesses, the batch's round requirement is determined by the maximum bank demand divided by that bank's service capacity, rounded up under the applicable rule. The most loaded bank constrains completion.

A mixed batch further separates total capacity from demand. Under modulo four, addresses 0, 4, 8, 12, 1, 2, 3 and 7 produce bank counts [4,1,1,2]. Eight requests divided by four one-port banks might suggest two rounds if demand were balanced. But B0 needs four services, so this batch requires four rounds under the model. B1 and B2 become idle after their first service, while unused capacity elsewhere cannot satisfy a B0 request. With two ports at each bank, the same demand can finish in two rounds.

A general implementation can have other prerequisites. The formula here is not a universal prediction of cycles for every cache operation. It is the result of the declared bank and port model.

Adding ports changes service within a bank

Now give each of the same four banks two read-service ports. Leave the data residency, mapping and request patterns unchanged.

Pattern P can serve two of its B0 requests per round and needs two rounds. Pattern Q still needs only one round; its original one-per-bank demand did not require the second ports.

The added ports therefore improve the overloaded bank case in this example without changing unique cache capacity or miss counts. They changed a service limit, not whether the four requested units were present.

The theoretical sum is eight port services per round across the four banks under this model. A batch concentrated on B0 cannot use all of that sum: its required bank has only two of those services.

Implementation cost, access duration and result-path limits would need another design analysis. Counting added ports does not supply a measured whole-program speedup.

How banked cache bandwidth depends on demand distribution

Use eight banks with one port each and redefine the stipulated mapping as a modulo eight. Pattern P's addresses 0, 4, 8 and 12 now map to B0, B4, B0 and B4. Each of those two banks has two requests, so the batch needs two rounds. The additional banks changed this pattern's distribution compared with modulo four.

But addresses 0, 8, 16 and 24 would all map to B0 under modulo eight. That four-request batch still needs four rounds with one port at that bank.

Additional banks still need an access pattern that uses their service capacity. The relation between the access pattern and mapping determines whether their available service can be used concurrently.

The DMA guide provides an access-path comparison for banked cache bandwidth. A CPU's current cached value does not establish that a noncoherent device can obtain it through its backing-memory path; that consuming path has its own visibility conditions. Here resident data is already valid for the local requests, and the unresolved question is simultaneous service at their banks. The device example does not supply bank counts, ports or throughput measurements. It reinforces the need to examine the actual consuming path after establishing where bytes reside.

Record unique resident bytes and available bank services separately. Each account needs its own inputs; a resident-byte total cannot supply the bank-service bound.

A different mapping changes which pattern conflicts

Return to four banks with one port each, but stipulate bank(a) as the integer part of a divided by four, then reduced modulo four. For addresses 0, 4, 8 and 12, the bank identities become B0, B1, B2 and B3.

That P pattern now needs one round under the same ready-access assumptions. Addresses 0, 1, 2 and 3 instead all fall in B0, so the original Q pattern now needs four rounds.

The mapping changed which access distribution is favourable. A graph showing one improved batch cannot establish that every workload became better.

The design also has to store and locate data consistently with its mapping. Relabelling requests on paper without the corresponding service arrangement would not establish a functioning cache.

This is a hypothetical comparison, not a method for inferring a vendor's hashing function or a recommendation for an undocumented address layout.

Other service limits can change the numerical result

The one-round Q calculation assumed the whole request batch could reach the banks and return without another shared bottleneck. Add a model-wide limit of two issued accesses per round, and the four Q requests need at least two issue rounds.

Bank independence still exists, but that new resource now limits the batch. A correct report must state which assumed limit changed rather than blame missing residency. Similarly, an access spanning several service partitions would need a defined demand rule. The initial one-bank-per-access assumption cannot silently cover a different width or operation.

These cases identify the scope of the simple calculation. They do not introduce eviction conflicts, DRAM row-buffer behaviour or prefetch usefulness as explanations for the original zero-miss bank model.

Verify residency and service demand separately

Preserve the initial resident units, access sequence, bank mapping and port capacity. Confirm the zero-miss assumption, then construct the bank-demand counts for that batch.

For modulo four with one port per bank, P has demand [4,0,0,0] and requires four rounds. Q has demand [1,1,1,1] and requires one. Two ports reduce P to two rounds without changing either demand vector.

A check that records only present data would miss the conflict. A check that records only total requests would miss their distribution. The result needs both the mapping and service constraints.

Keep modeled completion rounds distinct from a demonstrated processor measurement. The model can test the reasoning without establishing an implementation's actual cycle count.

Record the bank assignment for every symbolic request on the Lenovo IdeaPad laptop with an FHD touchscreen, listed at 15.6 inches. A 512GB PCIe SSD and an i5-1334U processor are named in its product description alongside 16GB DDR4. Keep the resident-data check separate from the demand vector [4,0,0,0] for P. The worksheet can reproduce four model service rounds; the listed hardware gives no evidence about that processor's actual banking.

Put the alternative mapping beside the original on the ASUS Vivobook 14 FHD laptop. The native description lists a Core 5 120U processor and 16GB DDR4 memory. For the same P and Q requests, changing from a modulo four to floor(a/4) modulo four reverses which batch concentrates in B0. Saving both address-to-bank tables keeps that change distinct from a measured machine speedup.